JojoS
October 19, 2020, 11:21am
21
Great, thanks for your feedback. This is some flaw in Mbed that should be fixed really soon, I have also searched a long time for this.
ARMmbed:master ← JojoS62:PR-fix-H7-USB
@ARMmbed/mbed-os-maintainers reviewers bot is not working as reported the last w… eek? Please review
and here is something about the LSE problem:
opened 01:33PM - 18 Oct 20 UTC
closed 08:15PM - 23 Feb 21 UTC
devices: st
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### Description of defect
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Activating the LSE clock may fail and throw an exception or LSE clock is not working or LSE clock is not stable with large jitter.
LSE clock is enabled for LPTimer (Mbed tickless and sleep mode wakeup), RTC clock and possibly other interfaces that can use the LSE clock.
The LSE clock typically uses a 32,768 kHz crystal and is automatically enabled on the first usage of LPTimer or RTC. There is a very large variety of crystals that can be used, a detailed description can be found in
https://www.st.com/resource/en/application_note/cd00221665-oscillator-design-guide-for-stm8afals-stm32-mcus-and-mpus-stmicroelectronics.pdf
For short, some devices use very tiny crystals with low load capcacitors to save (backup battery) power, some other use crystals with larger load capacitors for more stable clock.
This difference requires different driver currents, the tiny crystals need low current and can be damaged by higher currents. The crystals with larger capacitors require a higher current to start and run stable.
The default setting is the lowest driver load (DL) current, but this is not sufficient for many targets as they use crystals with higher capacities. The behaviour is random, LSE may work or produce no clock or clock with large jitter.
There is a setting necessary on targets that support adjusting the DL in the BDCR. There are HAL functions for this and in HAL examples, these are used already for some boards.
https://github.com/ARMmbed/mbed-os/blob/eb382989de046fc80859bc8bcf899458cd36ed9a/targets/TARGET_STM/TARGET_STM32H7/STM32Cube_FW/STM32H7xx_HAL_Driver/stm32h7xx_hal_rcc.h#L7445-L7475
It must be decided where to add this setting, it must be executed before the LSE is enabled.
LSE is in the backup power domain, so the LSE clock may be still active after a reset. In addition to the example code, it may be better to disable the LSE before changing the DL. Therefore, this setting can be placed also in system_clock.c, as it is more common than in lp_ticker or rtc_api.
Other issues that seems to be the same problem:
https://github.com/ARMmbed/mbed-os/issues/13127
https://github.com/ARMmbed/mbed-os/issues/13411
#### Target(s) affected by this defect ?
STM32 with adjustable driver load for LSE, e.g. :
F0 / F3 / F4_g2 / F7 / L0 / L4 / L4+ / L5 / G0 / G4 / H7 / WB / MP1
#### Toolchain(s) (name and version) displaying this defect ?
gcc-arm
not depending on toolchain
#### What version of Mbed-os are you using (tag or sha) ?
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mbed-os-6.3.0
#### What version(s) of tools are you using. List all that apply (E.g. mbed-cli)
mbed-cli
#### How is this defect reproduced ?
use RTC or LPTimer, enable MCO to monitor LSE frequency, e.g.
```
HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_LSE, RCC_MCODIV_1);
```
RCC_MCOx is target dependend.
