If the FPGA implementation isn’t accurate enough, how can I make sure of the ASIC compatibility with some device in gate level simulation, if there’s no HDL model for it (e.g., a BME280 sensor)?
If the FPGA implementation isn’t accurate enough, how can I make sure of the ASIC compatibility with some device in gate level simulation, if there’s no HDL model for it (e.g., a BME280 sensor)?