Number of cycles to schedule on Cortex-M

I am new and feel sorry to ask such a basic thing as an approximation to the maximum number of cycles to schedule a new task or interrupt.

I am looking for results for Cortex-M0+/M4/M7. I will need multiple of them. I was asked how many CPU takes the following:

  • Preempt low priority task and schedule high priority task.
  • Schedule from task to task on same priority.
  • Schedule from inactivated high priority task to low priority pending task.
  • Number of cycles from interrupt becoming active until first instruction of the user interrupt handler.
  • Schedule from end of interrupt back to the task preempted by this interrupt.
  • Schedule from end of interrupt to a task higher than the task that the interrupt has preempted.
  • How much adds an FPU?
  • How much adds an MMU/MPU?
  • I assume a typical configuration for an application has 16-64 tasks and 8 priority levels

Could someone help me out with this information?

Thanks for help