To reduce the system clock frequency you should modify the PLL coefficients in the /mbed/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/system_clock.c file.
The easiest way to figure out the target values is to use STM’s tool STM32MX, which you can download from the STM website for free.
Start a new project by clicking on the Access to board selector button:
In Categories on the Pinout & Configuration tab click on the RCC (Reset an Clock Control) item and for the High Speed CLock (HSE) select Crystal/Ceramic Resonator.
Proceed to the Clock Configuration tab. Make sure the Input frequency is set to 8 (MHz), HSE is selected as input for the PLL block and the PLLCLK is selected as source for the SYSCLK (System Clock).
Then start to vary the PLLM, PLLN and PLLR coefficients until you get the selected target SYSCLK.
Once you have succeeded (see in the picture above), modify accordingly the corresponding PLL coefficients in the file mbed/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/system_clock.c:
I want to use other clocks, (e.g. HSI or MSI), as SYSCLK source, because realized that power consumption of PLL is high.
Could you give me some advice what should I do to use HSI or MSI as SYSCLK source?
Why would you like to reduce the system clock from 80 MHz to 8 MHz?
Why did you decide to use different settings than advised? Those setting will not produce an 8 MHz system clock.
Do you have any ideas what should I do to use BufferedSerial in addition I did?
The working speed of peripherals depends on the system clock frequency. To get the desired bit rate of a UART (BufferedSerial) the mbed system software divides the system clock frequency by some predefined set of coefficients. If the system clock is too low than it could happen that the required bit rate cannot be achieved.
I want to use other clocks, (e.g. HSI or MSI), as SYSCLK source, because realized that power consumption of PLL is high.
Could you give me some advice what should I do to use HSI or MSI as SYSCLK source?
To use HSI as clock source add an mbed_app.json with the following content to your project:
Why would you like to reduce the system clock from 80MHz to 8 MHz?
For Reduce Power consumption.
Why did you decide to use different settings than advised? Those setting will not produce an 8 MHz system clock.
Because the nucleo-L476RG board does not have an external crystal to use HSE.
MSI is used for PLL in default setting of mbedOS, so I tried the configuration with MSI.
I think my setting can produce 8MHz system clock. But this setting did not work.
The working speed of peripherals depends on the system clock frequency. To get the desired bit rate of a UART ( BufferedSerial ) the mbed system software divides the system clock frequency by some predefined set of coefficients. If the system clock is too low than it could happen that the required bit rate cannot be achieved.
I asked STM if the 115.2kHz UART work on my settings, (e.g. 8MHz clock, 16 over sampling and so on), and got answer YES.
So I guessed the reason why UART did not work is there are some setting I should do in addition I did.
Unfortunately, I don’t know how to make it work without using the PLL block
OK. I understood the system clock setting of mbed assuming to use PLL block.
As a result, I could change SYSCLK from PLL to MSI and can set baud rate of UART.
However the setting of SYSCLK change back to PLL after ThisThread::sleep_for() function.
I guess the setting of SYSCLK is changed by callback function in sleep_for().
I want to know how to avoid to change back SYSCLK setting.
Could you give me some advice?