We have a problem downloading any *.hex onto the lpc55s69-evk USB mass storage device. The debug device has been updated with the latest lpc4322_bl_crc.bin and lpc4322_lpc55s69xpresso_if_crc.bin from https://os.mbed.com/teams/NXP/wiki/Updating-LPCXpresso-firmware. We have tried downloading from a Windows and from Linux computers. We have tried various *.hex files, prebuilt and built using online compiler and built by local mbed environment. We have tried on two individual lpc55s69-evk boards - no success on both.
The behavior is: As soon as the *.hex is copied to the “LPC55S69” USB device the software running on the Cortex 33 stops (e.g. a preprogrammed blinky stops) and nothing else happens. I’d have expected that the
Link2 boot LED is flashing. Mostly it stays dark, sometimes it just lights up. The copy process to the USB device does not get finished. If one waits long enough or presses the RESET button the FAIL.txt on the USB mass storage device contains: “Error: The interface firmware failedto reset/halt the target MCU”
The only thing that works is building and downloading using the NXP MCUxpresso IDE. This means the hardware is not the issue.
It pretty much looks like the lpc4322 on-board debugger cannot program the *.hex on the Cortex M33 flash. I suspect that the lpc4322_lpc55s69xpresso_if_crc.bin firmware does not do its job properly. Does anybody have a similar experience or knows how to fix this?
Some investigation updates: The https://github.com/ARMmbed/DAPLink software is the piece of debugger firmware running on the LPC4322 debug chip for flashing the LPC55S69.
The error “The interface firmware FAILED to initialize the target MCU” can only be caused by function lpc55s6x_target_set_state() in source/family/nxp/lpc55S6X/target_reset.c.
The target reset procedure for the LPC55S69 differs from the “standard” because the LPC55S69 has a (secure ?) Boot ROM which does not allow halting during its execution. The LPC55S69 manual says:
Traditionally, debug systems may set a vector catch at the reset vector in order to break
code execution at this point, however the LPC55S6x/LPC55S2x/LPC552x ROM prevents
this. To allow the debug system to halt execution immediately after the ROM has
completed preparations after a debug session request, a watch point may be set to trigger
on a read access to address 0x50000040.
Therefore function lpc55s6x_target_set_state() sets this watchpoint at 0x50000040 instead. Unfortunately, after issuing the CHIP_RESET_REQ:
// Reset using the debug mailbox
if (!swd_write_ap(DEBUGMB_CSW, 0x20)) {
return 0;
}
The target DP apparently does not respond successfully to SWD commands anymore. I suspect it always gets a “WAIT” status.
I managed to download the DAPLink SW and build it on my own. But I was not successful in my experiments with modifying the function mentioned above.
Does anybody have or know a repository with code for flashing the LPC55S69?
The problem is related to the silicon revision. Sorry, I don’t have an update if DAPLink was ever fixed for the new silicon.
I suggest visiting the NXP community forums to see if anyone has more information.
